In recent years, due to the wide-spread use of the Internet, cellular phone terminals, and the like, the amount of data communication has increased, and the communication traffic capacity handled by optical communication networks is increasing at a rate of four times in three years. In order to meet the demand for increased transmission capacity, a digital coherent optical communication technology that allows adoption of a high-transmission efficiency quadrature amplitude modulation (QAM) or the like is drawing attention.
The digital coherent optical communication technology needs, at a receiver, a local light in which the carrier waves are completely equal in frequency and phase (a local oscillating laser 201 in FIG. 2). However, in reality, it is very difficult to make equal the frequency and phase of the laser of a sender present at a different location and the frequency and phase of the laser of a receiver. Therefore, on electrical signals of a base band at the reception side, there occurs a non-zero intermediate frequency, in other words, a frequency offset. At present, the oscillatory frequency error of lasers used for commercial purposes is ±2.5 GHz at maximum, and therefore the frequency offset reaches a maximum of ±5 GHz.
As technologies for compensating this frequency offset in an optical communication system, there can be cited a method that uses an optical PLL (Phase Locked Loop), a method that compensates the frequency offset by digital signal processing, and the like. As a technology for compensating the frequency offset by digital signal processing, there are a method of NPL 1 and a method of PTL 1 (FIG. 2). FIG. 2 is a construction example of an optical digital coherent receiver based on digital signal processing. Input light mixes, in an optical frequency mixer 200, with light from a local oscillating laser 201, and travels to a PD (photodiode) 202 and an ADC (analog-digital converter) 203. In the method of PTL 1, a frequency offset estimator 207 calculates a frequency offset compensation amount, and a frequency offset compensator 204 carries out that compensation. In order to cancel out the phase added as an offset, the compensation is carried out by performing complex multiplication by a phase that has the same phase amount but is opposite in value to that phase.
At present, the speed of an optical communication that is being studied and developed is above 100 Gbps, but a digital signal processing unit 210 can be operated only at about several gigahertzes at highest. In order to fill this speed gap, arranging a plurality of the same circuits to carry out the compensation is adopted; for example, in the frequency offset compensator 204, a plurality of complex multipliers for multiplication by an opposite phase are arranged. More specifically, 100 or more complex multipliers are prepared, and the scale thereof is of an order of several megagates.
On the other hand, the digital signal processing unit 210 contains, besides this frequency offset compensator 204, various circuits such as an equalizer 205 that performs wavelength dispersion compensation, polarization separation, and the like, an integrator 206, a phase estimator 208 that estimates the phase of a carrier wave, and a data restoration 209. In particular, as for the wavelength dispersion compensation included in the equalizer 205, a time-domain FIR (Finite Impulse Response) filter is excessively large in circuit scale, and therefore the compensation is performed in frequency domain. Accordingly, an FFT (Fast Fourier Transform) that transforms data along a time axis into a frequency and an IFFT (Inverse Fast Fourier Transform) that performs a process opposite to the FFT are also included in the digital signal processing unit 210. Then, the size (the number of points) needed for the FFT or the IFFT varies depending on the wavelength dispersion compensation amount; the size is 4096 points, or needs to be about 16384 points when the amount to compensate is large.
As an efficient FFT/IFFT, butterfly computation based on Cooley-Tukey (NPL 2) is famous; however, the FFT/IFFT based on Cooley-Tukey, whose number of points is great, results in a complicated circuit. Therefore, division into two small FFTs/IFFTs based on a Prime Factor method (NPL 3) is adopted to perform processing. FIG. 3 is a diagram in which a 4096-point FFT/IFFT has been decomposed into two 64-point FFTs 302 by using the Prime Factor method.
In a digital coherent receiver of more than 100 Gbps, which is capable of processing if provided with 128 parallel, an FFT block 301 in FIG. 3 is mounted as a physical hardware component. However, in the description that follows, to simplify the description, 64 parallel (FFT block 300) is assumed instead of 128 parallel (FFT block 301) to give descriptions. Furthermore, each 64-point FFT may be decomposed into 8×8 by the method of Cooley-Tukey or other techniques, or also by the Prime Factor method.
Next, flow of data in FIG. 2 and, in particular, the order in which data are arranged will be described through the use of the drawings. FIG. 6 is an enlarged view exhibiting an analog/digital converter (hereinafter, ADC 203), a frequency offset compensator 204, and an equalizer 205 in FIG. 2. Inside the equalizer 205, there are included an FFT 602, a filter computation (complex multiplier) 603, and an IFFT 604 for performing the wavelength dispersion compensation in frequency domain. Furthermore, although not depicted in FIG. 6, many functions, such as polarization separation, are mounted.
First of all, arrangement of data in the ADC 203 will be described. Data output from a typical ADC 203 are as indicated in FIG. 4. Note that time 1 represents a sampling gap of the ADC. For example, in the case of an ADC 203 of 64 G samples/sec, the sampling interval is 15.625 ps (=1 sec/64 G samples), and therefore, time 1 is sampled waveform data at 15.625 ps, time 2 at 31.25 ps, and time 127 at 1984.375 (=127×15.625) ps. However, since the operating frequency of typical digital circuits is several gigahertzes at most, it is impossible to receive a piece of data in one clock cycle. Therefore, data output from the ADC 203 are given in an arrangement of 64 pieces in one clock cycle as in FIG. 4, and then are input to the digital signal processing unit 210.
On the other hand, as for data that need to be input to the FFTs, it can be understood from FIG. 3 that the data to be input in the 1st cycle are x[0], x[64], . . . x[63×64], and the data to be input in the 2nd cycle are x[1], x[65], . . . x[63×64+1]. Therefore, the order in which data are input to the FFTs is as in FIG. 5, which similarly applies to the case of IFFTs. Note that x represents an input signal to an FFT and y represents an output signal of an FFT. If FIG. 4 and FIG. 5 are compared, it can be understood that the outputs from the ADC and the inputs to the FFTs are different in order. Therefore, rearrangement of data is needed and, as in FIG. 6, a rearrangement-purpose memory (1) 601 and a rearrangement-purpose memory (2) 605 are needed.
Furthermore, similar rearranging is needed at a site where crossings are provided inside the FFTs (the rearrangement-purpose memory 303 in FIG. 3).
Hereinafter, data rearrangement inside an FFT in the case of a 64-parallel 4096-point FFT will be specifically described through the use of FIG. 7 and FIG. 8.
In order to perform rearrangement of data inside an FFT, a memory block as in FIG. 7 is prepared. This memory block is constructed of two sets (a rearrangement-purpose memory 303) in each of which 64 1R1W memories 701 whose width is an amount for one piece of data and whose depth is 64 words are arranged side by side (an arrangement 702 of 64 1R1W memories). Each 1R1W memory 701 is a typical 1R1W memory having a memory whose width is an amount for one piece of data and whose depth is 64 words (a memory capable of one reading process and one writing process in one cycle).
With respect to this memory block, values are written in at positions indicated in the upper-side diagram in FIG. 8. In FIG. 8, [A, B] indicates an output of a left-side FFT array in FIG. 3. In other words, 64 values [0, 0], [0, 1], . . . [0, 63] calculated in the 1st cycle are written in at positions on a diagonal line where entries have been given in boldface in the upper-side diagram in FIG. 8. Likewise, [1, 0], [1, 1], . . . [1, 63] in the 2nd cycle are sequentially written into the upper-side memory in FIG. 8. Such an operation is continually performed 64 times to fill the memory. Conversely, at the time of readout, the readout is performed at positions enclosed by a dotted line in the upper-side diagram in FIG. 8. Due to this, readout of [*, 0] (* is a value of 0 to 63) is performed in the 1st cycle, and readout of [*, 1] is performed in the 2nd cycle. Thus, data can be appropriately given to the FFT array on the right side in FIG. 3. In this manner, the use of 64 memories and the contrivance regarding the positions to write data as in the upper diagram in FIG. 8 makes it possible to realize the rearrangement by using only a memory capacity for one frame of the FFT (4096 pieces of data).
However, since overwrite occurs during readout from a memory, two memory sets (arrangements 702 of 64 1R1W memories) are prepared as illustrated in FIG. 7. Then, for the first writing-in, the upper-side memory group is written into, and then the lower-side memory group is written into, and then the upper-side memory group. In this manner, the writing-in is performed in order. On the other hand, at the readout side, readout is performed in the opposite order, so that the overwrite problem can be solved.
Next, the case where the frequency offset compensation is performed in frequency domain will be considered. When the offset compensation is performed in frequency domain, the offset compensation is realized by a shift to the left or right by an amount for the offset as in FIG. 9. Therefore, assuming that a signal y is a result of the FFT, it suffices that when a shift by p (p is an integer) to the left is performed, y[(n−p)%4096] (% indicates the remainder when n−p is divided by 4096) is calculated, and when a shift by p to the right is performed, y[(n+p)%4096] is calculated. In other words, when a right shift by 1 is performed, it suffices that the handling of a result of the FFT as follows: y[4095] as y[0], y[0] as y[1], y[1] as y[2], and so on, is carried out. However, as seen from FIG. 5, y[4095] is output in the 64th cycle, and in order to handle y[4095] as y[0], and y[0] as y[1], a delay of at least 64 cycles or more is needed. In other words, a mere shift to right by 1 requires a memory capable of retaining at least 4096 pieces of data, and such memories are needed in an amount of several hundred kilogates.